SH7615 Datasheet, PDF (824/925 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH
RISC engine Family/SH7600 Series

Table 20.3 Register States in Standby Mode
Module
Registers Initialized
Registers
Registers that Retain with Undefined
Data
Contents
Interrupt controller (INTC)
—
All registers
—
User break controller (UBC) —
All registers
—
Bus state controller (BSC)
—
All registers
—
Direct memory access
controller (DMAC)
DMA channel control • DMA source address —
register 0, 1
registers 0 and 1
DMA operation register • DMA destination
address registers 0
and 1
• DMA transfer count
registers 0 and 1
• DMA request/
response selection
control registers 0
and 1
• Vector number setting
registers DMA0 and
DMA1
Watchdog timer (WDT)
Bits 7 to 5 of the timer Bits 2 to 0 of the timer —
control/status register control/status register
Reset control/status
register
Timer counter
16-bit free-running timer (FRT) All registers
—
—
Serial communication interface All registers
—
—
with FIFO (SCIF1 to SCIF2)
Serial I/O (SIO0 to SIO2)
—
All registers
—
High-performance user
—
debugging interface (H-UDI)
All registers
—
16-bit timer pulse unit (TPU) —
All registers
—
Pin function controller (PFC) —
All registers
—
Ethernet controller direct
All registers
—
—
memory access controller
(E-DMAC)
Ethernet controller (EtherC) All registers
—
—
Others
—
Standby control
—
registers 1 and 2
Frequency modification
register
Rev. 2.00, 03/05, page 786 of 884