SH7615 Datasheet, PDF (641/925 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH
RISC engine Family/SH7600 Series

Initialization
Clear TE and RE bits
to 0 in SCSCR
Set TFRST and RFRST bits
to 1 in SCFCR
Set CKE1 and CKE0 bits
in SCSCR (leaving TE and
[1]
RE bits cleared to 0)
Set transmit/receive format
in SCSMR
[2]
Set value in SCBRR
[3]
Wait
1-bit interval elapsed?
No
Yes
Set RTRG1–0 and TTRG1–0 bits
in SCFCR, and clear TFRST
and RFRST bits to 0
Set TE or RE bit to 1 in SCSCR,
and set RIE, TIE, and MPIE bits ^[4]
[1] Set the clock selection in SCSCR.
Be sure to clear bits RIE, TIE, and
MPIE, and bits TE and RE, to 0.
When clock output is selected in
asynchronous mode, it is output
immediately after SCSCR settings are
made.
Select input or output for the SCK pin
with the PFC.
[2] Set the transmit/receive format in
SCSMR.
When using IrDA mode, also set
SCIFMR.
[3] Write a value corresponding to the bit
rate into the bit rate register (SCBRR).
(Not necessary if an external clock is
used.)
[4] Wait at least one bit interval, then set
the TE bit or RE bit in SCSCR to 1.
Also set the RIE, TIE, and MPIE bits.
Setting the TE and RE bits enables
the TxD and RxD pins to be used.
When transmitting, the SCIF will go to
the mark state; when receiving, it will
go to the idle state, waiting for a start
bit.
End
Figure 14.4 Sample SCIF Initialization Flowchart
• Serial Data Transmission (Asynchronous Mode)
Figure 14.5 shows a sample flowchart for serial transmission.
Use the following procedure for serial data transmission after enabling the SCIF for
transmission.
Rev. 2.00, 03/05, page 603 of 884