SH7615 Datasheet, PDF (247/925 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH
RISC engine Family/SH7600 Series

6.2.4 Break Address Register B (BARB)
BARBH
Bit:
Initial value:
R/W:
15
BAB31
0
R/W
14
BAB30
0
R/W
13
BAB29
0
R/W
12
BAB28
0
R/W
11
BAB27
0
R/W
10
BAB26
0
R/W
9
BAB25
0
R/W
8
BAB24
0
R/W
Bit:
Initial value:
R/W:
7
BAB23
0
R/W
6
BAB22
0
R/W
5
BAB21
0
R/W
4
BAB20
0
R/W
3
BAB19
0
R/W
2
BAB18
0
R/W
1
BAB17
0
R/W
0
BAB16
0
R/W
BARBL
Bit:
Initial value:
R/W:
15
BAB15
0
R/W
14
BAB14
0
R/W
13
BAB13
0
R/W
12
BAB12
0
R/W
11
BAB11
0
R/W
10
BAB10
0
R/W
9
BAB9
0
R/W
8
BAB8
0
R/W
Bit:
Initial value:
R/W:
7
BAB7
0
R/W
6
BAB6
0
R/W
5
BAB5
0
R/W
4
BAB4
0
R/W
3
BAB3
0
R/W
2
BAB2
0
R/W
1
BAB1
0
R/W
0
BAB0
0
R/W
Break address register B (BARB) consists of two 16-bit readable/writable registers: break address
register BH (BARBH) and break address register BL (BARBL). BARBH specifies the upper half
(bits 31 to 16) of the address used as a channel B break condition, and BARBL specifies the lower
half (bits 15 to 0). BARBH and BARBL are initialized to H'0000 by a power-on reset; after a
manual reset, their values are undefined.
BARBH Bits 15 to 0—Break Address B31 to B16 (BAB31 to BAB16): These bits store the upper
half (bits 31 to 16) of the address used as a channel B break condition.
BARBL Bits 15 to 0—Break Address B15 to B0 (BAB15 to BAB0): These bits store the lower
half (bits 15 to 0) of the address used as a channel B break condition.
Rev. 2.00, 03/05, page 209 of 884