SH7615 Datasheet, PDF (621/925 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH
RISC engine Family/SH7600 Series

Bit 3—Multiprocessor bit (MPB): When reception is performed using a multiprocessor format in
asynchronous mode, MPB stores the multiprocessor bit in the receive data.
The MPB flag is read-only and cannot be modified.
Bit 3: MPB
Description
0
Data with a 0 multiprocessor bit has been received^*
(Initial value)
1
Data with a 1 multiprocessor bit has been received
Note: * Retains its previous state when the RE bit is cleared to 0 while using a multiprocessor
format.
Bit 2—Multiprocessor Bit Transfer (MPBT): When transmission is performed using a
multiprocessor format in asynchronous mode, MPBT stores the multiprocessor bit to be added to
the transmit data.
The MPBT bit setting is invalid in synchronous mode and IrDA mode, when a multiprocessor
format is not used, and when the operation is not transmission.
Bit 2: MPBT
0
1
Description
Data with a 0 multiprocessor bit is transmitted
Data with a 1 multiprocessor bit is transmitted
(Initial value)
Bit 1—Receive Data Error Ignore Enable (EI): Selects whether or not the receive operation is to
be continued when a framing error or parity error occurs in receive data (ER = 1).
Bit 1: EI
Description
0
Receive operation is halted when framing error or parity error occurs during
reception (ER = 1)
(Initial value)
1
Receive operation is continued when framing error or parity error occurs during
reception (ER = 1)
Note: When EI = 0, only the last data in SCFRDR is treated as data containing an error. When EI
= 1, receive data is sent to SCFRDR even if it contains an error.
Rev. 2.00, 03/05, page 583 of 884