SH7615 Datasheet, PDF (704/925 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH
RISC engine Family/SH7600 Series

Bits 7 to 5—Counter Clear 2 to 0 (CCLR2 to CCLR0): These bits select the TCNT counter
clearing source.
Channel
0
Bit 7:
CCLR2
0
1
Bit 6:
CCLR1
0
1
0
1
Bit 5:
CCLR0
0
1
0
1
0
1
0
1
Description
TCNT clearing disabled
(Initial value)
TCNT cleared by TGRA compare match/input
capture
TCNT cleared by TGRB compare match/input
capture
TCNT cleared by counter clearing for another
channel performing synchronous
clearing/synchronous operation ^*1
TCNT clearing disabled
TCNT cleared by TGRC compare match/input
capture ^*2
TCNT cleared by TGRD compare match/input
capture ^*2
TCNT cleared by counter clearing for another
channel performing synchronous
clearing/synchronous operation ^*1
Bit 7:
Bit 6:
Channel Reserved^*3 CCLR1
Bit 5:
CCLR0
Description
1, 2
0
0
0
TCNT clearing disabled
(Initial value)
1
TCNT cleared by TGRA compare match/input
capture
1
0
TCNT cleared by TGRB compare match/input
capture
1
TCNT cleared by counter clearing for another
channel performing synchronous clearing/
synchronous operation ^*1
Notes: 1. Synchronous operation setting is performed by setting the SYNC bit in TSYR to 1.
2. When TGRC or TGRD is used as a buffer register, TCNT is not cleared because the
buffer register setting has priority, and compare match/input capture does not occur.
3. Bit 7 is reserved in channels 1 and 2. It is always read as 0. The write value should
always be 0.
Rev. 2.00, 03/05, page 666 of 884