SH7615 Datasheet, PDF (361/925 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH
RISC engine Family/SH7600 Series

7.5.11 64-Mbit Synchronous DRAM (2 Mwords × 32 Bits) Connection
64-Mbit Synchronous DRAM (2 Mwords × 32 Bits) Connection Example: Figure 7.34 shows
an example connection between the SH7615 and 64-Mbit synchronous DRAM (2 Mwords × 32
bits).
This LSI
A22
A13
A12
2 Mword ×
32-bit SDRAM
A12
A11
A10
A2
CKIO
CKE
CSn
RAS
CAS/OE
RD/WR
D31
A0
CLK
CKE
CS
RAS
CAS
WE
I/O31
D0
DQMUU/WE3
DQMUL/WE2
DQMLU/WE1
DQMLL/WE0
I/O0
DQMUU
DQMUL
DQMLU
DQMLL
Figure 7.34 64-Mbit Synchronous DRAM (2 Mwords × 32 Bits) Connection Example
Bus Status Controller (BSC) Register Settings: Set the individual bits in the memory control
register (MCR) as follows.
MCR (bit 6) SZ = 1
MCR (bit 7) AMX2 = 0
MCR (bit 5) AMX1 = 0
MCR (bit 4) AMX0 = 0
Synchronous DRAM Mode Settings: To make mode settings for the synchronous DRAM, write
to address X + H'FFFF0000 or X + H'FFFF8000 from the CPU. (X represents the setting value.)
Whether to use X + H'FFFF0000 or X + H'FFFF8000 determines on the synchronous DRAM
used.
Rev. 2.00, 03/05, page 323 of 884