SH7615 Datasheet, PDF (763/925 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH
RISC engine Family/SH7600 Series

Contention between TGR Read and Input Capture: If the input capture signal is generated in
the T₁ state of a TGR read cycle, the data that is read will be the data before input capture transfer.
Figure 16.49 shows the timing in this case.
Pφ
Address
Read signal
Input capture
signal
TGR
Internal
data bus
TGR read cycle
T₁
T₂
TGR address
N
M
N
Figure 16.49 Contention between TGR Read and Input Capture
Rev. 2.00, 03/05, page 725 of 884