SH7615 Datasheet, PDF(603/925 Page) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7600 Series

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SH7615 Datasheet, PDF (603/925 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7600 Series

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14.1.2 Block Diagrams

A block diagram of the SCIF is shown in figure 14.1, and a diagram of the IrDA block in figure

14.2.

Module data bus

Internal

data bus

SCFRDR

(16-stage)

RxD

SCRSR

TxD

SCK

Parity check

SCFTDR

(16-stage)

SCTSR

SCFDR

SCFCR

SC1SSR

SC2SSR

SCSCR

SCSMR

SCFER

SCIMR

Transmission/

reception control

Parity generation

SCBRR

Baud rate

generator

Clock

PÏ

PÏ/4

PÏ/16

PÏ/64

SCIF

External clock

BRI

TxI

RxI

ERI

IrDA/SCI switchover (to IrDA block)

SCRSR:

SCFRDR:

SCTSR:

SCFTDR:

SCSMR:

SCSCR:

Receive shift register

Receive FIFO data register

Transmit shift register

Transmit FIFO data register

Serial mode register

Serial control register

SC1SSR:

SC2SSR:

SCBRR:

SCFCR:

SCFDR:

SCFER:

SCIMR:

Serial status 1 register

Serial status 2 register

Bit rate register

FIFO control register

FIFO data count register

FIFO error register

IrDA mode register

Figure 14.1 Block Diagram of SCIF

Rev. 2.00, 03/05, page 565 of 884

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