SH7615 Datasheet, PDF (40/925 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH
RISC engine Family/SH7600 Series

Table 1.1 Features
Item
CPU
Specifications
• Original Renesas Technology architecture
• 32-bit internal architecture
• General register machine
 Sixteen 32-bit general registers
 Six 32-bit control registers (including 3 added for DSP use)
 Ten 32-bit system registers
• RISC (Reduced Instruction Set Computer) type instruction set
 Fixed 16-bit instruction length for improved code efficiency
 Load-store architecture (basic operations are executed between
registers)
 Delayed branch instructions reduce pipeline disruption during
branches
 C-oriented instruction set
• Instruction execution time: One instruction per cycle (16.0 ns/instruction at
62.5 MHz operation)
• Address space: Architecture supports 4 Gbytes
• On-chip multiplier: Multiply operations (32 bits × 32 bits → 64 bits) and
multiply-and-accumulate operations (32 bits × 32 bits + 64 bits → 64 bits)
executed in two to four cycles
• Five-stage pipeline
Rev. 2.00, 03/05, page 2 of 884