SH7615 Datasheet, PDF (23/925 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH
RISC engine Family/SH7600 Series

Item
Page Revisions (See Manual for Details)
21.3.8 Serial I/O Timing 848
Table 21.13 Serial I/O
Timing
21.3.11 Ethernet
853
Controller Timing
Table 21.16 Ethernet
Controller Timing
21.3.12 STATS, BH, and 856
BUSHiZ Signal Timing
Table 21.17 STATS, BH,
and BUSHiZ Signal
Timing
Figure 21.78 STATS 856
Output Timing
Figure 21.79 BH Output
Timing
A.1 Addresses
859
Table 21.13 amended
Item
SRCK, STCK clock input cycle time
Symbol
tsIcyc
Min
tPcyc or^*
66.7
Max
—
Unit
ns
Table 21.16 amended
Item
TX-CLK cycle time
RX-CLK cycle time
Symbol
t_Tcyc
t
Rcyc
Min Typ Max Unit
40
—
—
ns
40
—
—
ns
Figure
21.61
Figure
21.71
Table 21.17 amended
Item
Symbol Min Typ Max Unit Figure
STATS1 and STATS0 output delay time tSTATd
—
—
16
ns
21.78
Figure 21.78 and Figure 21.79 amended
(Before) G-DMAC → (After) DMAC
SICTR2 amended
Address
Register
Name
Bit 7
H'FFFFFC24 SICTR2 —
H'FFFFFC25
—
Bit 6
—
TM
Bit 5
—
SE
Bit Names
Bit 4
—
DL
Bit 3
—
TIE
Bit 2
—
RIE
Bit 1
—
TE
Bit 0
—
RE
Module
SIO2
862
864
SCSMR1 amended
Address
Register
Name
H'FFFF FCC0 SCSMR1
Bit 7
C/A
Bit Names
Bit 6
Bit 5
Bit 4
Bit 3
CHR/ICK3 PE/ICK2 O/E/ICK1 STOP/
ICK0
Bit 2
MP
Bit 1
CKS1
Bit 0
CKS0
Module
SCIF1
EESR amended
Address
Register
Name
Bit 7
H'FFFF FD14 EESR
—
H'FFFF FD15
—
H'FFFF FD16
—
H'FFFF FD17
RMAF
Bit 6
—
ECI
—
—
Bit 5
—
TC
—
—
Bit Names
Bit 4
Bit 3
—
—
TDE
TFUF
ITF
CND
RRF
RTLF
Bit 2
TABT
FR
DLC
RTSF
Bit 1
RABT
RDE
CD
PRE
Bit 0
Module
RFCOF E-DMAC
RFOF
TRO
CERF
TRSCER amended
Address
Register
Name
Bit 7
Bit 6
H'FFFF FD1C TRSCER —
—
H'FFFF FD1D
—
—
H'FFFF FD1E
—
—
H'FFFF FD1F
RMAFCE —
Bit 5
—
—
—
—
Bit Names
Bit 4
Bit 3
—
—
—
—
—
—
—
—
Bit 2
—
—
—
—
Bit 1
—
—
—
—
Bit 0
—
—
—
—
Module
E-DMAC
Rev. 2.00, 03/05, page xxiii of xxxviii