SH7615 Datasheet, PDF (14/925 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH
RISC engine Family/SH7600 Series

Item
Page
7.5.11 64-Mbit
325
Synchronous DRAM (2
Mword × 32 Bit)
Connection
Figure 7.36 128-Mbit
Synchronous DRAM (8
Mwords × 16 Bits)
Connection Example
Figure 7.37 256-Mbit 326
Synchronous DRAM (8
Mwords × 32 Bits)
Connection Example
7.11.3 Preventing Wrong 358
Data Output to
Synchronous DRAM
8.2.1 Cache Control
361
Register (CCR)
Bit 4—Cache Purge Bit
(CP)
9.2.1 EtherC Mode
384
Register (ECMR)
9.2.8 PHY Interface
391
Status Register (PSR)
9.3.1 Transmission
405
9.5 Usage Notes
416
10.2.2 E-DMAC Transmit 422
Request Register
(EDTRR)
10.2.3 E-DMAC Receive 423
Request Register
(EDRRR)
Revisions (See Manual for Details)
• 128-Mbit Synchronous DRAM (8 Mwords × 16 Bits)
Connection Example
Figure 7.36 added
• 256-Mbit Synchronous DRAM (8 Mwords × 32 Bits)
Connection Example
Figure 7.37 added
Section 7.11.3 added
Description added
... the CP bit reverts to 0. The CP bit always reads 0. Read the
cache to check if initialization is completed.
Bit 1—Duplex Mode (DM)
Note added
Note: When internal loopback mode is specified (ILB = 1),
full-duplex transfer (DM = 1) must be used.
The duplex mode information (half-duplex or full-duplex)
detected by the PHY-LSI must be set to the DM bit. If this
setting does not match the duplex mode in the PHY-LSI, the
transfer rate may be degraded or a data collision may occur.
Note added
Note: The LMON bit is cleared to 0 when the LNKSTA pin is
at a high level, and is set to 1 when the pin is at a low level.
Description amended
4. After waiting for the frame interval time (9.6 µs for 10Base
or 0.96 µs for 100Base), the transmitter enters the idle state,
and if there is more transmit data, continues transmitting.
Section 9.5 added
Note added
For details on writing to the register, see section 10.4, Usage
Notes.
Note added
For details on writing to the register, see section 10.4, Usage
Notes.
Rev. 2.00, 03/05, page xiv of xxxviii