SH7615 Datasheet, PDF (156/925 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH
RISC engine Family/SH7600 Series

• Modes 0 to 6
PLL circuits 1 and 2 halted
EXTAL input or crystal resonator used (modes 0 to 3)
CKIO input (modes 4 to 6)
FR3
FR2
FR1
FR0
φ
0
0
0
0
×1
0
1
0
0
×1
0
1
0
1
×1
0
1
1
0
×1
1
0
0
0
×1
1
0
0
1
×1
1
0
1
0
×1
1
1
0
0
×1
1
1
1
0
×1
1
1
1
1
×1
Iφ
Eφ
Pφ
CKIO
×1/4
×1/4
×1/4
×1
×1/2
×1/4
×1/4
×1
×1/2
×1/2
×1/4
×1
×1/2
×1/2
×1/2
×1
×1
×1/4
×1/4
×1
×1
×1/2
×1/4
×1
×1
×1/2
×1/2
×1
×1
×1
×1/4
×1
×1
×1
×1/2
×1
×1
×1
×1
×1
Note: Do not use combinations other than those shown above.
Frequency Change: When PLL circuit 1 or PLL circuit 2 becomes operational after modifying
the frequency modification register (including modification the frequency modification register in
the operating state), access the frequency modification register using the following procedure, and
noting the cautions listed below.
Frequency change procedure
• Set the on-chip watchdog timer (WDT) overflow time to secure the PLL circuit oscillation
settling time (CKS2 to CKS0 bits in WTCSR).
• Clear the WT/IT and TME bit to 0 in WTCSR.
• Perform a read anywhere in an external memory area 0 to 4 cache-through area.
• Change the frequency modification register to the target frequency, or change the
operating/halted state of the PLL circuits 1 and 2 (the clocks will stop temporarily inside the
chip).
• The oscillation circuits operate, and the clock is supplied to the WDT. This clock increments
the WDT.
• On WDT overflow, supply of a clock with the frequency set in frequency setting bits FR3 to
FR0 begins. In this case, the OVF bit in WTSCR and the WOVF bit in RSTCSR are not set, an
interval timer interrupt (ITI) is not requested, and the WDTOVF signal is not asserted.
Sample code for changing the frequency is shown below.
Rev. 2.00, 03/05, page 118 of 884