SH7615 Datasheet, PDF (677/925 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH
RISC engine Family/SH7600 Series

When Using Synchronous Internal Clock Mode: In reception, note that if RE is cleared to zero
1.5 peripheral operating clock cycles after the rising edge of the RxD D7 bit SCK output, RDF
will be set to 1 but copying to SCFRDR will not be possible.
When Using the DMAC: When an external clock source is used as the serial clock, the transmit
clock should not be input until at least 5 Pφ clock cycles after SCFTDR is updated by the DMAC.
Incorrect operation may result if the transmit clock is input within 4 Pφ cycles after SCFTDR is
updated. (See figure 14.26.)
When performing SCFRDR reads by the DMAC, be sure to set the relevant SCIF receive-FIFO-
data-full interrupt (RXI) as an activation source.
SCK
t
TDFE
TXD
D0
D1
D2
D3
D4
D5
D6
Figure 14.26 Example of Synchronous Transmission by DMAC
SCFRDR Reading and the RDF Flag: The RDF flag in the serial status 1 register (SC1SSR) is
set when the number of receive data bytes in the receive FIFO data register (SCFRDR) has
become equal to or greater than the receive trigger number set by bits RTRG1 and RTRG0 in the
FIFO control register (SCFCR). After RDF is set, receive data equivalent to the trigger number
can be read from SCFRDR, allowing efficient continuous reception.
However, if the number of data bytes in SCFRDR is equal to or greater than the trigger number,
the RDF flag will be set to 1 again if it is cleared to 0. RDF should therefore be cleared to 0 after
being read as 1 after receive data has been read to reduce the number of data bytes in SCFRDR to
less than the trigger number.
The number of receive data bytes in SCFRDR can be found from the lower 8 bits of the FIFO data
count register (SCFDR).
Rev. 2.00, 03/05, page 639 of 884