SH7615 Datasheet, PDF (55/925 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH
RISC engine Family/SH7600 Series

Type
System
control
Symbol
RES
I/O
Input
Name
Reset
WDTOVF
BGR
Output
Output
Watchdog
timer overflow
Bus grant
BRLS
Input Bus release
Operating
mode
Interrupts
Bus control
MD0 to MD4 Input
NMI
Input
to IRL3 IRL0 Input
IVECF
Output
BS
Output
Mode setting
Nonmaskable
interrupt
External
interrupt
request input
0 to 3
Interrupt
vector fetch
cycle
Bus cycle
start
CS4 to CS0 Output
WAIT
RD
RAS
Input
Output
Output
Chip select
0 to 4
Wait
Read
Row address
strobe
Function
When RES = 0 and NMI = 1, the chip
enters the power-on reset state. When
RES = 0 and NMI = 0, the chip enters the
manual reset state
Counter overflow signal output in
watchdog timer mode
Indicates that the bus has been released
to an external device. The device that
output the BRLS signal recognizes that
the bus has been acquired when it
receives the BGR signal
Driven low when an external device
requests release of the bus
The operating mode is specified by the
levels at these pins
Inputs the nonmaskable interrupt request
signal
These pins input maskable interrupt
request signals
Indicates an external vector read cycle
Signal indicating the start of a bus cycle
Asserted every data cycle in burst
transfer
Chip select signals indicating the area
being accessed
Wait state request signal
Strobe signal indicating a read cycle
DRAM/synchronous DRAM RAS signal
Rev. 2.00, 03/05, page 17 of 884