SH7615 Datasheet, PDF (168/925 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH
RISC engine Family/SH7600 Series

3. The vector numbers and vector table address offsets for each on-chip peripheral
module interrupt are given table 5.4, Interrupt Exception Vectors and Priorities, in
section 5, Interrupt Controller.
4. Vector numbers are set in the on-chip vector number register. See section 5.3, Register
Descriptions, in section 5, Interrupt Controller, and section 11, Direct Memory Access
Controller, for more information.
5. The same vector number, 10, is generated for a DMAC DMA address error and an E-
DMAC DMA address error. (See table 4.3 (a).)
Both the address error flag (AE) in the DMAC’s DMA operation register (DMAOR) and
the address error control bit (AEC) in the E-DMAC’s E-DMAC operation control register
(EDOCR) must therefore be read in the exception service routine to determine which
DMA address error has occurred.
Table 4.4 Calculating Exception Vector Table Addresses
Exception Source
Vector Table Address Calculation
Power-on reset
Manual reset
(Vector table address) = (vector table address offset)
= (vector number) × 4
Other exception handling
(Vector table address) = VBR + (vector table address offset)
= VBR + (vector number) × 4
Note: VBR: Vector base register
Vector table address offset: See table 4.3.
Vector number: See table 4.3.
Rev. 2.00, 03/05, page 130 of 884