SH7615 Datasheet, PDF (880/925 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH
RISC engine Family/SH7600 Series

21.3.5 Free-Running Timer Timing
Table 21.9 Free-Running Timer Timing
Conditions: V_CC = PLLV_CC = 3.3 V ±0.3 V, PV_CC = 5.0 V ± 0.5 V/3.3 V ±0.3 V, PV_CC ≥ V_CC,
V_SS = PV_SS = PLLV_SS = 0 V, Ta = –20 to +75°C
Item
Output compare output delay time
Input capture input setup time
(t_Ecyc:t_Pcyc = 1:1)
Input capture input setup time
(t_Ecyc:t_Pcyc = 1:2)
Input capture input setup time
(t_Ecyc:t_Pcyc = 1:4)
Input capture input hold time
Timer clock input setup time
(t_Ecyc:t_Pcyc = 1:1)
Timer clock input setup time
(t_Ecyc:t_Pcyc = 1:2)
Timer clock input setup time
(t_Ecyc:t_Pcyc = 1:4)
Timer clock pulse width
(single edge specified)
Timer clock pulse width
(both edges specified)
Symbol Min
t_FOCD
—
t_FICS
50
Max
100
—
t_FICS
t_cyc + 50 —
t_FICS
3t_cyc + 50 —
t_FICH
50
—
t_FCKS
50
—
t_FCKS
t_cyc + 50 —
t_FCKS
3t_cyc + 50 —
t_{FCKW H}
4.5
—
t_{FCKW L}
8.5
—
Unit Figure
ns 21.49, 21.50
ns 21.49
ns 21.50
ns 21.50
ns 21.49, 21.50
ns 21.51
ns 21.52
ns 21.52
t_Pcyc 21.51, 21.52
t_Pcyc
CKIO
t_FOCD
FTOA, FTOB
FTI
t_FICS t_FICH
Figure 21.49 FRT Input/Output Timing (t_Ecyc:t_Pcyc = 1:1)
Rev. 2.00, 03/05, page 842 of 884