SH7615 Datasheet, PDF (69/925 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH
RISC engine Family/SH7600 Series

Table 1.4 Power-Down State
State
Mode
Entering
Conditions Clock
CPU
On-chip
Supporting
Modules
CPU
Registers
On-Chip
Cache or
On-Chip
RAM
Exiting
Conditions
Sleep
mode
Executing
SLEEP
instruction
while SBY bit
is cleared in
SBYCR1
Operating
Halted
Operating Held
Held
1. Interrupt
2. DMA address
error
3. Power-on reset
4. Manual reset
Standby
mode
Executing
SLEEP
instruction
while SBY
bit is set in
SBYCR1
Halted
Halted
Halted and Held
initialized^*1
Undefined 1. NMI interrupt
2. Power-on reset
3. Manual reset
Module
standby
function
Setting
Operating
MSTP bit
corresponding
to individual
module
Operating
(DSP
halted)
Clock supply
to specified
module
halted,
module
initialized^*2
Held
Held
1. Clearing MSTP
bit
2. Power-on reset
3. Manual reset
Notes: 1. Depends on individual supporting module or pin.
2. DMAC and DSP registers and specified module interrupt vectors retain their set values.
Rev. 2.00, 03/05, page 31 of 884