SH7615 Datasheet, PDF (511/925 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH
RISC engine Family/SH7600 Series

Bit 5—DREQn Level Bit (DL): Selects the DREQn input detection level. The DL bit is initialized
to 0 by a reset and in standby mode. Its value is retained during a module standby.
Bit 5: DL
0
1
Description
When DS is 0, DREQ is detected by low level; when DS is 1, DREQ is
detected at falling edge
(Initial value)
When DS is 0, DREQ is detected by high level; when DS is 1, DREQ is
detected at rising edge
Bit 4—Transfer Bus Mode Bit (TB): Selects the bus mode for DMA transfers. When 1 (burst
mode) is set to bit TB, set 1 (edge detection) to the DREQ select bit (DS). When 1 is set to bit TB
and 0 (level detection) is set to bit DS, system operations are not guaranteed. The TB bit is
initialized to 0 by a reset and in standby mode. Its value is retained during a module standby.
Bit 4: TB
0
1
Description
Cycle-steal mode
Burst mode
(Initial value)
Bit 3—Transfer Address Mode Bit (TA): Selects the DMA transfer address mode. The TA bit is
initialized to 0 by a reset and in standby mode. Its value is retained during a module standby.
Bit 3: TA
0
1
Description
Dual address mode
Single address mode
(Initial value)
Bit 2—Interrupt Enable Bit (IE): Determines whether or not to request a CPU interrupt at the end
of a DMA transfer. When the IE bit is set to 1, an interrupt (DEI) request is sent to the CPU when
the TE bit is set. The IE bit is initialized to 0 by a reset and in standby mode. Its value is retained
during a module standby.
Bit 2: IE
0
1
Description
Interrupt request disabled
Interrupt request enabled
(Initial value)
Bit 1—Transfer-End Flag Bit (TE): Indicates that the transfer has ended. When the value in the
DMA transfer count register (TCR) becomes 0, the DMA transfer ends normally and the TE bit is
set to 1. When TCR is not 0, the TE bit is not set if the transfer ends because of an NMI interrupt
or DMA address error, or because the DME bit in the DMA operation register (DMAOR) or the
DE bit was cleared. To clear the TE bit, read 1 from it and then write 0. When the TE bit is set,
setting the DE bit to 1 will not enable a transfer. The TE bit is initialized to 0 by a reset and in
standby mode. Its value is retained during a module standby.
Rev. 2.00, 03/05, page 473 of 884