SH7615 Datasheet, PDF (685/925 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH
RISC engine Family/SH7600 Series

15.2.1 Receive Shift Register (SIRSR)
Bit: 15
14
13
...
3
2
1
0
...
Initial value: —
—
—
...
—
—
—
—
R/W: —
—
—
...
—
—
—
—
SIRSR is a 16-bit register used to receive serial data. The data is fetched in MSB first from the
SRxD pin in synchronization with the fall of the serial receive clock (SRCK), and is shifted into
SIRSR. The data length is set by the transmit/receive data length select bit (DL) in the
corresponding serial control register (SICTR). When data transfer to SIRSR is completed, the data
contents are automatically transferred to the receive data register (SIRDR), and the receive data
register full flag (RDRF) is set in the serial status register (SISTR).
If the next data word input operation ends before the RDRF flag is cleared, an overrun error
occurs, the receive overrun error flag (RERR) is set in SISTR, and an overrun error signal is sent
to the interrupt controller (INTC). The data in SIRSR overwrites the data in SIRDR.
15.2.2 Receive Data Register (SIRDR)
Bit: 15
14
13
...
3
2
1
0
...
Initial value: 0
0
0
...
0
0
0
0
R/W: R
R
R
...
R
R
R
R
SIRDR is a 16-bit register that stores serial receive data. When data is transferred from SIRSR to
SIRDR, the receive data register full flag (RDRF) is set in the serial status register (SISTR). If the
receive interrupt enable flag (RIE) is set in SICTR, a receive-data-full interrupt (RDFI) request is
sent to the interrupt controller (INTC) and the DMA controller (DMAC). When the flag is cleared,
this interrupt request signal is not generated. When SIRDR is read by the DMAC, the RDRF flag
is cleared automatically. SIRDR is initialized to H'0000 by a reset.
Rev. 2.00, 03/05, page 647 of 884