SH7615 Datasheet, PDF(767/925 Page) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7600 Series

English

English German Russian Spanish Italian Polish Chinese Japanese Korean French Portuguese	Language :

SH7615 Datasheet, PDF (767/925 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7600 Series

◁

Contention between TCNT Write and Overflow/Underflow: If there is an up-count or down-

count in the T2 state of a TCNT write cycle, and overflow/underflow occurs, the TCNT write takes

precedence and the TCFV/TCFU flag in TSR is not set .

Figure 16.53 shows the operation timing in the case of contention between a TCNT write and

overflow.

TCNT write cycle

T1

T2

PÏ

Address

TCNT address

Write signal

TCNT

H'FFFF

TCNT write data

M

TCFV flag

Disabled

Figure 16.53 Contention between TCNT Write and Overflow

Multiplexing of I/O Pins: In the Chip, the TCLKA input pin is multiplexed with the TIOCC0 I/O

pin, the TCLKB input pin with the TIOCD0 I/O pin, the TCLKC input pin with the TIOCB1 I/O

pin, and the TCLKD input pin with the TIOCB2 I/O pin. When an external clock is input,

compare match output should not be performed from a multiplexed pin.

Interrupts and Module Stop Mode: If module stop mode is entered when an interrupt has been

requested, it will not be possible to clear the CPU interrupt source or DMAC activation source.

Interrupts should therefore be disabled before entering module stop mode.

Rev. 2.00, 03/05, page 729 of 884

▷