SH7615 Datasheet, PDF (305/925 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH
RISC engine Family/SH7600 Series

7.2.5 Wait Control Register 2 (WCR2)
Bit: 15
14
13
A4WD1 A4WD0 —
Initial value: 0
0
0
R/W: R/W R/W
R
12
A4WM
0
R/W
11
A3WM
0
R/W
10
A2WM
0
R/W
9
A1WM
0
R/W
8
A0WM
0
R/W
Bit: 7
6
5
4
3
2
1
0
—
—
—
—
IW41 IW40 W41 W40
Initial value: 0
0
0
0
1
0
1
1
R/W: R
R
R
R
R/W R/W R/W R/W
Bits 15 and 14—Number of External Waits Specification for Area 4 (A4WD1, A4WD0): These
bits specify the number of cycles between acceptance of CS4 space external wait negation and RD
or WEn negation.
Bit 15: A4WD1
0
1
Bit 14: A4WD0
0
1
0
1
Description
1 cycle
2 cycles
4 cycles
Reserved (do not set)
(Initial value)
Bit 13—Reserved bit. This bit is always read as 0. The write value should always be 0.
Bits 12 to 8—External Wait Mask Specification for Areas 0 to 4 (A4WM to A0WM): These bits
enable waits to be masked for CS spaces 0 to 4. When a value other than 00 is set in the wait
control bits for CS spaces 0 to 4 (W41 to W00), external wait input can be enabled, but the wait
input can be masked by setting these bits to 1. With synchronous DRAM, external wait input is
ignored regardless of the settings.
Rev. 2.00, 03/05, page 267 of 884