SH7615 Datasheet, PDF (271/925 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH
RISC engine Family/SH7600 Series

Bit 10—PC Break Select C (PCBC): Selects whether a channel C instruction fetch cycle break is
effected before or after execution of the instruction.
Bit 10: PCBC
0
1
Description
Channel C instruction fetch cycle break is effected before instruction execution
(Initial value)
Channel C instruction fetch cycle break is effected after instruction execution
Bits 9 and 8—Reserved: These bits are always read as 0. The write value should always be 0.
Bit 7—CPU Condition Match Flag D (CMFCD): This flag is set to 1 when a CPU bus cycle
condition, among the break conditions set for channel D, is satisfied. This flag is not cleared to 0
(if the flag setting is to be checked again after it has once been set, the flag must be cleared by a
write).
Bit 7: CMFCD
0
1
Description
User break interrupt has not been generated by a channel D CPU cycle
condition
(Initial value)
User break interrupt has been generated by a channel D CPU cycle condition
Bit 6—DMAC Condition Match Flag D (CMFPD): This flag is set to 1 when a DMAC bus cycle
condition, among the break conditions set for channel D, is satisfied. This flag is not cleared to 0
(if the flag setting is to be checked again after it has once been set, the flag must be cleared by a
write).
Bit 6: CMFPD
0
1
Description
User break interrupt has not been generated by a channel D on-chip DMAC
cycle condition
(Initial value)
User break interrupt has been generated by a channel D on-chip DMAC cycle
condition
Bit 5—Execution-Times Break Enable D (ETBED): Enables a channel D execution-times break
condition. When this bit is 1, a user break interrupt is generated when the number of break
conditions that have occurred equals the number of executions specified by the break execution
times register (BETRD).
Bit 5: ETBED
0
1
Description
Channel D execution-times break condition is disabled
Channel D execution-times break condition is enabled
(Initial value)
Bit 4—Reserved: This bit is always read as 0. The write value should always be 0.
Rev. 2.00, 03/05, page 233 of 884