SH7615 Datasheet, PDF (396/925 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH
RISC engine Family/SH7600 Series

7.11.2 When Using Iφ:Eφ Clock Ratio of 1:1, 8-Bit Bus Width, and External Wait Input
When using an Iφ:Eφ clock ratio of 1:1 and an 8-bit bus width, at least 1.5 address hold cycles
should be set.
Set a value other than the initial value in bits AnSHW1, AnSHW0, A4HW1, and A4HW0 for the
relevant space.
7.11.3 Preventing Wrong Data Output to Synchronous DRAM
In SDRAM burst write mode and bank active mode, wrong data may be output to SDRAM when
the Ethernet controller direct memory access controller (E-DMAC) performs DMA reception by
using SDRAM as the receive buffer, when the direct memory access controller (DMAC) performs
16-bit transmission to SDRAM (destination address), or when the cache controller performs write-
back to SDRAM.
Conditions: When all of the following conditions are satisfied, the previous data written to
SDRAM is erroneously output to the SDRAM as the first four bytes of the 16-byte SDRAM write
data.
• The clock ratio of external clock (Eφ):internal clock (Iφ) is not set to 1:1.
• SDRAM burst write mode is used.
• SDRAM bank active mode is used.
• The E-DMAC performs DMA reception by using SDRAM as the receive buffer, the DMAC
performs 16-byte transfer (source address = on-chip memory or on-chip peripheral module
space, and destination address = SDRAM), or the cache controller performs write-back to
SDRAM.
Countermeasures: This problem in SDRAM burst write mode is avoided by any of the following
countermeasures.
• Set the clock ratio of external clock (Eφ): internal clock (Iφ) to 1:1.
• Specify SDRAM auto-precharge mode.
Rev. 2.00, 03/05, page 358 of 884