SH7615 Datasheet, PDF (702/925 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH
RISC engine Family/SH7600 Series

16.1.4 Register Configuration
Table 16.3 shows the register configuration of the TPU.
Table 16.3 Register Configuration
Channel Name
Abbreviation R/W
0
Timer control register 0 TCR0
R/W
Timer mode register 0 TMDR0
R/W
Timer I/O control
register 0H
TIOR0H
R/W
Timer I/O control
register 0L
TIOR0L
R/W
Timer interrupt enable TIER0
register 0
Timer status register 0 TSR0
R/W
R/(W)^*
Timer counter 0
TCNT0
R/W
Timer general register TGR0A
R/W
0A
Timer general register TGR0B
R/W
0B
Timer general register TGR0C
R/W
0C
Timer general register TGR0D
R/W
0D
1
Timer control register 1 TCR1
R/W
Timer mode register 1 TMDR1
R/W
Timer I/O control
TIOR1
R/W
register 1
Timer interrupt enable TIER1
register 1
Timer status register 1 TSR1
R/W
R/(W)^*
Timer counter 1
TCNT1
R/W
Timer general register TGR1A
R/W
1A
Timer general register TGR1B
R/W
1B
Initial
Value
H'00
H'C0
H'00
H'00
H'40
H'C0
H'0000
H'FFFF
H'FFFF
H'FFFF
H'FFFF
H'00
H'C0
H'00
H'40
H'C0
H'0000
H'FFFF
H'FFFF
Address
Access
size (Bits)
H'FFFFFC50 8,16
H'FFFFFC51 8,16
H'FFFFFC52 8,16
H'FFFFFC53 8,16
H'FFFFFC54 8,16
H'FFFFFC55
H'FFFFFC56
H'FFFFFC58
8,16
16
16
H'FFFFFC5A 16
H'FFFFFC5C 16
H'FFFFFC5E 16
H'FFFFFC60
H'FFFFFC61
H'FFFFFC62
8,16
8,16
8,16
H'FFFFFC64 8,16
H'FFFFFC65
H'FFFFFC66
H'FFFFFC68
8,16
16
16
H'FFFFFC6A 16
Rev. 2.00, 03/05, page 664 of 884