SH7615 Datasheet, PDF (587/925 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH
RISC engine Family/SH7600 Series

Section 13 Watchdog Timer (WDT)
13.1 Overview
A single-channel watchdog timer (WDT) is provided on-chip for monitoring system operations. If
WDTOVF ^{a system becomes uncontrolled and the timer counter overflows without being rewritten correctly}
by the CPU, an overflow signal (
) is output externally. The WDT can simultaneously
generate an internal reset signal for the entire chip.
When this watchdog function is not needed, the WDT can be used as an interval timer. In the
interval timer operation, an interval timer interrupt is generated at each counter overflow. The
WDT is also used when recovering from standby mode, in modifying a clock frequency, and in
clock pause mode.
13.1.1 Features
The WDT includes the following features.
• Can be switched between watchdog timer mode and interval timer mode.
WDTOVF •
output in watchdog timer mode
WDTOVF The
signal is output externally when the counter overflows, and a simultaneous
internal reset of the chip can also be selected (either a power-on reset or manual reset can be
specified).
• Interrupt generation in interval timer mode
An interval timer interrupt is generated when the counter overflows.
• Used when standby mode is cleared or the clock frequency is changed, and in clock pause
mode.
• Choice of eight counter input clocks
Rev. 2.00, 03/05, page 549 of 884