SH7615 Datasheet, PDF (17/925 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH
RISC engine Family/SH7600 Series

Item
13.2.3 Reset
Control/Status Register
(RSTCSR)
13.4.4 System Reset
with WDTOVF
Figure 13.9 Example of
Circuit for System Reset
with WDTOVF Signal
Page
553,
554
561
Revisions (See Manual for Details)
Description amended
RSTCR is initialized to H'1E by input of a reset signal from the
RES pin, but is not initialized by the internal reset signal
generated by overflow of the WDT. It is initialized to H'1E in
standby mode, and in clock pause mode.
Figure 13.9 amended
This LSI
Reset input
RES
Reset signal to
entire system
WDTOVF
13.4.6 Internal Reset by
Watchdog Timer (WDT) in
Sleep Mode
14.2.6 Serial Control 574
Register (SCSCR)
14.2.9 Bit Rate Register 587,
(SCBRR)
588
Table 14.3 Examples of
Bit Rates and SCBRR
Settings in Asynchronous
Mode
Section 13.4.6 added
Bit 6—Receive Interrupt Enable (RIE)
Description amended
Bit 6—Receive Interrupt Enable (RIE): Enables or disables
generation of receive-FIFO-data full interrupt (RXI), receive-
error interrupt (ERI), and break interrupt (BRI) requests when,
after serial receive data is transferred from the receive shift
register (SCRSR) to the receive FIFO data register
(SCFRDR), the number of data bytes in SCFRDR reaches or
exceeds the receive trigger set number, and the RDF flag is
set to 1 in SC1SSR.
Table 14.3 amended
Pφ (MHz)
12
30
nN
Error
(%)
nN
Error
(%)
2 212 0.03 3 132 0.13
2 155 0.16 3 97 –0.35
2 77 0.16 2 194 0.16
1 155 0.16 2 97 –0.35
1 77 0.16 1 194 0.16
0 155 0.16 1 97 –0.35
0 77 0.16 0 194 0.16
0 38 0.16 0 97 –0.35
0 19 –2.34 0 48 –0.35
0 11 0.00 0 29 0.00
0 9 –2.34 0 23 1.73
Rev. 2.00, 03/05, page xvii of xxxviii