SH7615 Datasheet, PDF (278/925 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH
RISC engine Family/SH7600 Series

6.3.4 Saved Program Counter (PC) Value
1. When instruction fetch (pre-instruction-execution) is set as break condition
The program counter (PC) value saved to the stack in user break interrupt exception handling
is the address of the instruction for which the break condition matched. In this case, the fetched
instruction is not executed, a user break interrupt being generated prior to its execution. If a
setting is made for an instruction following an instruction for which interrupts are prohibited,
the break is effected before execution of the next instruction at which interrupts are accepted,
so that the saved PC value is the address at which the break occurs.
2. When instruction fetch (post-instruction-execution) is set as break condition
The program counter (PC) value saved to the stack in user break interrupt exception handling
is the address of the next instruction to be executed after the instruction for which the break
condition matched. In this case, the fetched instruction is executed, and a user break interrupt
is generated before execution of the next instruction. However, if a setting is made for an
instruction for which interrupts are prohibited, the break is effected before execution of the
next instruction at which interrupts are accepted, so that the saved PC value is the address at
which the break occurs.
3. When data access (CPU/on-chip DMAC) is set as break condition
The value saved is the start address of the next instruction after the instruction for which
execution has been completed when user break exception handling is initiated.
When data access (CPU/on-chip DMAC) is set as a break condition, the point at which the
break is to be made cannot be specified. A break is effected before execution of the instruction
about to be fetched around the time of the break data access.
6.3.5 X Memory Bus or Y Memory Bus Cycle Break
A break condition for an X bus cycle or Y bus cycle can only be specified for channel C or D.
When XYEC in BBRC or XYED in BBRD is set to 1, break addresses and break data on the X
memory bus or Y memory bus are selected. Either the X memory bus or the Y memory bus must
be selected with the XYSC bit in BBRC or the XYSD bit in BBRD; the X and Y memory buses
cannot both be included in the break conditions at the same time. The break conditions are applied
to X memory bus cycles or Y memory bus cycles by setting the CPU bus master, data access
cycle, read or write access, and word operand size or no operand size specification.
When an X memory address is selected as a break condition, specify the X memory address in the
upper 16 bits of BARC and BAMRC or BARD and BAMRD; when a Y memory address is
selected, specify the Y memory address in the lower 16 bits of BARC and BAMRC or BARD and
BAMRD. The same method is used to specify X memory data or Y memory data for BDRC and
BDMRC or BDRD and BMRD.
Rev. 2.00, 03/05, page 240 of 884