SH7615 Datasheet, PDF(757/925 Page) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7600 Series

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SH7615 Datasheet, PDF (757/925 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7600 Series

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PÏ

TCNT

input clock

TCNT

(underflow)

Underflow signal

H'0000

H'FFFF

TCFU flag

TCIU interrupt

Figure 16.41 TCIU Interrupt Setting Timing

Status Flag Clearing Timing: After a status flag is read as 1 by the CPU, it is cleared by writing

0 to it. When the DMAC is activated, the flag is cleared automatically. Figure 16.42 shows the

timing for status flag clearing by the CPU, and figure 16.43 shows the timing for status flag

clearing by the DMAC.

TSR write cycle

T1

T2

PÏ

Address

TSR address

Write signal

Status flag

Interrupt

request

signal

Figure 16.42 Timing for Status Flag Clearing by CPU

Rev. 2.00, 03/05, page 719 of 884

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