SH7615 Datasheet, PDF (606/925 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH
RISC engine Family/SH7600 Series

14.2 Register Descriptions
With the exception of the IrDA mode register (SCIMR) and bits 6 to 3 (ICK3 to ICK0) of the
serial mode register (SCSMR), IrDA communication mode settings are the same as for
asynchronous mode.
14.2.1 Receive Shift Register (SCRSR)
Bit: 7
6
5
4
3
2
1
0
R/W: —
—
—
—
—
—
—
—
The receive shift register (SCRSR) is the register used to receive serial data.
The SCIF sets serial data input from the RxD pin in SCRSR in the order received, starting with the
LSB (bit 0) or MSB (bit 7), and converts it to parallel data. When one byte of data has been
received, it is transferred to the receive FIFO data register (SCFRDR) automatically.
SCRSR cannot be read or written to directly.
14.2.2 Receive FIFO Data Register (SCFRDR)
Bit: 7
6
5
4
3
2
1
0
R/W: R
R
R
R
R
R
R
R
The receive FIFO data register (SCFRDR) is a 16-stage FIFO register (8 bits per stage) that stores
received serial data.
When the SCIF has received one byte of serial data, it transfers the received data from SCRSR to
SCFRDR where it is stored, and completes the receive operation. SCRSR is then enabled for
reception, and consecutive receive operations can be performed until the receive FIFO data
register is full (16 data bytes).
SCFRDR is a read-only register, and cannot be written to.
If a read is performed when there is no receive data in the receive FIFO data register, an undefined
value will be returned. When the receive FIFO data register is full of receive data, subsequent
serial data is lost.
Rev. 2.00, 03/05, page 568 of 884