SH7615 Datasheet, PDF (592/925 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH
RISC engine Family/SH7600 Series

RES a reset signal from the pin, but is not initialized by the internal reset signal generated by
overflow of the WDT. It is initialized to H'1E in standby mode, and in clock pause mode.
Bit 7—Watchdog Timer Overflow Flag (WOVF): Indicates that WTCNT has overflowed (from
H'FF to H'00) in watchdog timer mode. It is not set in interval timer mode.
Bit 7: WOVF
0
1
Description
No WTCNT overflow in watchdog timer mode
Cleared by reading WOVF, then writing 0 in WOVF
Set by WTCNT overflow in watchdog timer mode
(Initial value)
Bit 6—Reset Enable (RSTE): Selects whether to reset the chip internally if WTCNT overflows in
watchdog timer mode.
Bit 6: RSTE
0
1
Description
Not reset when WTCNT overflows
(Initial value)
LSI not reset internally, but WTCNT and WTCSR reset within WDT
Reset when WTCNT overflows
Bit 5—Reset Select (RSTS): Selects the type of internal reset generated if WTCNT overflows in
watchdog timer mode.
Bit 5: RSTS
0
1
Description
Power-on reset
Manual reset
(Initial value)
Bits 4 to 1—Reserved: These bits are always read as 1. The write value should always be 1.
Bit 0— Reserved: This bit is always read as 0. The write value should always be 0.
13.2.4 Notes on Register Access
The watchdog timer’s WTCNT, WTCSR, and RSTCSR registers differ from other registers in that
they are more difficult to write. The procedures for writing and reading these registers are given
below.
Writing to WTCNT and WTCSR: These registers must be written by a word transfer
instruction. They cannot be written by byte or longword transfer instructions. WTCNT and
WTCSR both have the same write address. The write data must be contained in the lower byte of
the written word. The upper byte must be H'5A (for WTCNT) or H'A5 (for WTCSR) (figure 13.2).
This transfers the write data from the lower byte to WTCNT or WTCSR.
Rev. 2.00, 03/05, page 554 of 884