SH7615 Datasheet, PDF (561/925 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH
RISC engine Family/SH7600 Series

Countermeasures:
(1) Countermeasure against malfunction in DMA transfer on channel 1 by an on-chip
peripheral module request
This problem is avoided by the following countermeasure.
(a) Set the DMAC priority mode to fixed priority mode.
14. DMAC does not perform DMA transfer between on-chip memory and on-chip peripheral
module by an external request
Phenomenon:
(1) DMAC does not perform DMA transfer between on-chip memory and on-chip peripheral
module by an external request.
When the on-chip DMAC is set to external request (DREQ) mode and cycle-steal mode
and DMA transfer is attempted between on-chip memory and on-chip peripheral module or
between on-chip peripheral modules, the DMAC may not perform DMA transfer for the
second and later DREQ inputs.
Conditions:
(1) Conditions for malfunction in DMA transfer between on-chip memory and on-chip
peripheral module by an external request
When the following conditions are all satisfied, the DMAC does not perform DMA transfer
between on-chip memory and on-chip peripheral module or between on-chip peripheral
modules by an external request.
(a) The external request (DREQ) is selected for the transfer request source.
(b) The DMA transfer between on-chip memory and on-chip peripheral module or between
on-chip peripheral modules is selected.
(c) Cycle-steal mode is used.
Countermeasures:
(1) Countermeasure against malfunction in DMA transfer between on-chip memory and on-
chip peripheral module by an external request
This problem is avoided by the following counter measure.
(a) Do not select the external request (DREQ) for the transfer request source.
15. Data bus collision during single-address DMAC transfer
Phenomenon:
(1) Data bus collision during DMA transfer in single address mode
In the system which includes the SH7615, an external device with DACK, and
synchronous DRAM (SDRAM), if single-address DMA transfer is performed from the
external device with DACK to SDRAM immediately after the SH7615 writes data to
SDRAM, the SH7615 may erroneously drive data bus during the single-address DMA
transfer , and the erroneously driven data may collide with the DMA transfer data.
Rev. 2.00, 03/05, page 523 of 884