SH7615 Datasheet, PDF (177/925 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH
RISC engine Family/SH7600 Series

4.6 When Exception Sources Are Not Accepted
When an address error or interrupt is generated after a delayed branch instruction or interrupt-
disabled instruction, it is sometimes not immediately accepted but is stored instead, as described in
table 4.10. When this happens, it will be accepted when an instruction for which exception
acceptance is possible is decoded.
Table 4.10 Exception Source Generation Immediately after a Delayed Branch Instruction
or Interrupt-Disabled Instruction
Exception Source
Point of Occurrence
Immediately after a delayed branch instruction^*1
Immediately after an interrupt-disabled instruction^*2
Address Error
Not accepted
Accepted
Interrupt
Not accepted
Not accepted
A repeat loop comprising up to three instructions (instruction Not accepted
fetch cycle not generated)
Not accepted
First instruction or last three instructions in a repeat loop
containing four or more instructions
Fourth from last instruction in a repeat loop containing four or Accepted
more instructions
Not accepted
Notes: 1. Delayed branch instructions: JMP, JSR, BRA, BSR, RTS, RTE, BF/S, BT/S, BSRF,
BRAF
2. Interrupt-disabled instructions: LDC, LDC.L, STC, STC.L, LDS, LDS.L, STS, STS.L
4.6.1 Immediately after a Delayed Branch Instruction
When an instruction placed immediately after a delayed branch instruction (delay slot) is decoded,
neither address errors nor interrupts are accepted. The delayed branch instruction and the
instruction located immediately after it (delay slot) are always executed consecutively, so no
exception handling occurs between the two.
4.6.2 Immediately after an Interrupt-Disabled Instruction
When an instruction immediately following an interrupt-disabled instruction is decoded, interrupts
are not accepted. Address errors are accepted.
Rev. 2.00, 03/05, page 139 of 884