SH7615 Datasheet, PDF (663/925 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH
RISC engine Family/SH7600 Series

Initialization
[1]
[1] PFC initialization: Set the RxD pin,
and the SCK pin if necessary, with
the PFC.
Start of reception
[2] Receive error handling: If a
receive error occurs, read the
ORER flag in SC2SSR, and after
Read ORER flag in SC2SSR
performing the appropriate error
handling, clear the ORER flag to
0. Transmission/reception cannot
ORER = 1?
Yes
[2]
be resumed if the ORER flag is
set to 1.
[3] SCIF status check and receive
No
Error handling
data read: Read the serial status 1
register (SC1SSR) and check that
Read RDF flag in SC1SSR ^[3]
RDF = 1, then read receive data
from the receive FIFO data
register (SCFRDR) and clear the
No
RDF = 1?
RDF flag to 0. Transition of the
RDF flag from 0 to 1 can also be
identified by an RXI interrupt.
Yes
Read receive data
from SCFRDR, and clear RDF ^[4]
flag to 0 in SC1SSR
No
All data received?
Yes
Clear RE bit to 0 in SCSCR
[4] Serial reception continuation
procedure: To continue serial
reception, read at least the receive
trigger set number of data bytes
from SCFRDR, and write 0 to the
RDF flag after reading 1 from it.
The number of receive data bytes
in SCFRDR can be ascertained by
reading the lower 8 bits of the
FIFO data count register
(SCFDR). (The RDF bit is cleared
automatically when the DMAC is
activated by an RXI interrupt and
the SCFRDR value is read.)
End of reception
Figure 14.20 Sample Serial Reception Flowchart (1)
Rev. 2.00, 03/05, page 625 of 884