SH7615 Datasheet, PDF (744/925 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH
RISC engine Family/SH7600 Series

16.4.6 Phase Counting Mode
In phase counting mode, the phase difference between two external clock inputs is detected and
TCNT is incremented/decremented accordingly. This mode can be set for channels 1, and 2.
When phase counting mode is set, an external clock is selected as the counter input clock and
TCNT operates as an up/down-counter regardless of the setting of bits TPSC2 to TPSC0 and bits
CKEG1 and CKEG0 in TCR. However, the functions of bits CCLR1 and CCLR0 in TCR, and of
TIOR, TIER, and TGR are valid, and input capture/compare match and interrupt functions can be
used.
When overflow occurs while TCNT is counting up, the TCFV flag in TSR is set; when underflow
occurs while TCNT is counting down, the TCFU flag is set.
The TCFD bit in TSR is the count direction flag. Reading the TCFD flag provides an indication of
whether TCNT is counting up or down.
Table 16.7 shows the correspondence between external clock pins and channels.
Table 16.7 Phase Counting Mode Clock Input Pins
Channels
When channel 1 is set to phase counting mode
When channel 2 is set to phase counting mode
A-Phase
TCLKA
TCLKC
External Clock Pins
B-Phase
TCLKB
TCLKD
Example of Phase Counting Mode Setting Procedure: Figure 16.25 shows an example of the
phase counting mode setting procedure.
Phase counting mode
Select phase counting mode 1
1 Select phase counting mode with bits MD3
to MD0 in TMDR.
2 Set the CST bit in TSTR to 1 to start the
count operation.
Start count
2
<Phase counting mode>
Figure 16.25 Example of Phase Counting Mode Setting Procedure
Rev. 2.00, 03/05, page 706 of 884