SH7615 Datasheet, PDF (243/925 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH
RISC engine Family/SH7600 Series

6.2 Register Descriptions
6.2.1 Break Address Register A (BARA)
BARAH
Bit:
Initial value:
R/W:
15
BAA31
0
R/W
14
BAA30
0
R/W
13
BAA29
0
R/W
12
BAA28
0
R/W
11
BAA27
0
R/W
10
BAA26
0
R/W
9
BAA25
0
R/W
8
BAA24
0
R/W
Bit:
Initial value:
R/W:
7
BAA23
0
R/W
6
BAA22
0
R/W
5
BAA21
0
R/W
4
BAA20
0
R/W
3
BAA19
0
R/W
2
BAA18
0
R/W
1
BAA17
0
R/W
0
BAA16
0
R/W
BARAL
Bit:
Initial value:
R/W:
15
BAA15
0
R/W
14
BAA14
0
R/W
13
BAA13
0
R/W
12
BAA12
0
R/W
11
BAA11
0
R/W
10
BAA10
0
R/W
9
BAA9
0
R/W
8
BAA8
0
R/W
Bit:
Initial value:
R/W:
7
BAA7
0
R/W
6
BAA6
0
R/W
5
BAA5
0
R/W
4
BAA4
0
R/W
3
BAA3
0
R/W
2
BAA2
0
R/W
1
BAA1
0
R/W
0
BAA0
0
R/W
Break address register A (BARA) consists of two 16-bit readable/writable registers: break address
register AH (BARAH) and break address register AL (BARAL). BARAH specifies the upper half
(bits 31 to 16) of the address used as a channel A break condition, and BARAL specifies the lower
half (bits 15 to 0). BARAH and BARAL are initialized to H'0000 by a power-on reset; after a
manual reset, their values are undefined.
BARAH Bits 15 to 0—Break Address A31 to A16 (BAA31 to BAA16): These bits store the upper
half (bits 31 to 16) of the address used as a channel A break condition.
BARAL Bits 15 to 0—Break Address A15 to A0 (BAA15 to BAA0): These bits store the lower
half (bits 15 to 0) of the address used as a channel A break condition.
Rev. 2.00, 03/05, page 205 of 884