SH7615 Datasheet, PDF (764/925 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH
RISC engine Family/SH7600 Series

Contention between TGR Write and Input Capture: If the input capture signal is generated in
the T₂ state of a TGR write cycle, the input capture operation takes precedence and the write to
TGR is not performed.
Figure 16.50 shows the timing in this case.
Pφ
Address
TGR write cycle
T₁
T₂
TGR address
Write signal
Input capture
signal
TCNT
M
TGR
M
Figure 16.50 Contention between TGR Write and Input Capture
Rev. 2.00, 03/05, page 726 of 884