SH7615 Datasheet, PDF (656/925 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH
RISC engine Family/SH7600 Series

Figure 14.15 shows an example of SCIF operation for multiprocessor format reception.
1
Serial
data
Start
bit Data (ID1)
0 D0 D1
Stop Start
MPB bit bit Data (Data1)
D7 1 1 0 D0 D1
Stop
MPB bit
1
D7 0
1 Idle state
(mark state)
MPIE
RDF
SCFRDR value
ID1
RXI interrupt request
(multiprocessor interrupt)
MPIE = 0
SCFRDR data read
and RDF flag cleared
to 0 by RXI interrupt
handler
As data is not this
station’s ID,
MPIE bit is set
to 1 again
(a) Data does not match station’s ID
RXI interrupt request
is not generated,
and SCFRDR
retains its state
1
Serial
data
Start
bit Data (ID2)
0 D0 D1
Stop Start
MPB bit bit Data (Data2)
D7 1 1 0 D0 D1
Stop
MPB bit
1
D7 0
1 Idle state
(mark state)
MPIE
RDF
SCFRDR value
ID1
ID2
Data2
RXI interrupt request
(multiprocessor interrupt)
MPIE = 0
SCFRDR data read
and RDF flag cleared
to 0 by RXI interrupt
handler
As data matches this
station’s ID, reception
continues and data is
received by RXI
interrupt handler
(b) Data matches station’s ID
MPIE bit set
to 1 again
Figure 14.15 Example of SCIF Receive Operation
(Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit, LSB-First Transfer)
Rev. 2.00, 03/05, page 618 of 884