SH7615 Datasheet, PDF (293/925 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH
RISC engine Family/SH7600 Series

Signal
With Bus
I/O
Released Description
DREQ1
Input Input
DMA request 1
DACK1
Output Output DMA acknowledge 1
REFOUT Output Output Refresh execution request output when bus is released
DQMUU/
WE3
Output Hi-Z
When synchronous DRAM is used, connected to DQM pin for
the most significant byte (D31 to D24). For ordinary space,
indicates writing to the most significant byte
DQMUL/
WE2
Output Hi-Z
When synchronous DRAM is used, connected to DQM pin for
the second byte (D23 to D16). For ordinary space, indicates
writing to the second byte
DQMLU/
WE1
Output Hi-Z
When synchronous DRAM is used, connected to DQM pin for
the third byte (D15 to D8). For ordinary space, indicates writing
to the third byte
DQMLL/
WE0
CAS3
CAS2
CAS1
CAS0
Output Hi-Z
Output Hi-Z
Output Hi-Z
Output Hi-Z
Output Hi-Z
When synchronous DRAM is used, connected to DQM pin for
the least significant byte (D7 to D0). For ordinary space,
indicates writing to the least significant byte
When DRAM is used, connected to CAS pin for the most
significant byte (D31 to D24)
When DRAM is used, connected to CAS pin for the second
byte (D23 to D16)
When DRAM is used, connected to CAS pin for the third byte
(D15 to D8)
When DRAM is used, connected to CAS pin for the least
significant byte (D7 to D0)
STATS0,
STATS1
Output Output
BUSHIZ Input Input
Bus master identification 00: CPU
01: DMAC
10: E-DMAC
11: Other
Signal used in combination with WAIT signal to place bus and
strobe signals in the high-impedance state without the ending
bus cycle.
Note: Hi-Z: High impedance
Rev. 2.00, 03/05, page 255 of 884