SH7615 Datasheet, PDF (499/925 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH
RISC engine Family/SH7600 Series

10.4 Usage Notes
10.4.1 E-DMAC Transmit Request Register (EDTRR) and E-DMAC Receive Request
Register (EDRRR) Usage Notes
Phenomenon: If the transmit and receive descriptor active bit has the “inactive” setting, the
EDTRR register: TR bit (Transmit Request) and the EDRRR register: RR bit (Receive Request)
are cleared and the operation of transmit DMAC is halted.
When the timing of clear TR/RR request bit and set TR/RR request bit by user’s firmware are
matched, E-DMAC can’t recognize the exact condition of TR/RR bit.
Condition: When TR/RR request bit is always set by the firmware without checking the state of
TR/RR request bit.
Countermeasures: Please check the TR/RR request bit is cleared by E-DMAC first, and then set
the TR/RR request bit by user’s firmware.
(1) There are two ways to check TR request bit that is cleared by E-DMAC.
(a) Possible to check read “0” of TR bit of E-DMAC directly.
(b) Possible to check read “1” of TDE (Transmit Descriptor Exhausted) in EESR resister after
the interrupt on.
(2) There are two ways to check RR request bit that is cleared by E-DMAC.
(a) Possible to check read “0” of RR bit of E-DMAC directly.
(b) Possible to check read “1” of RDE (Receive Descriptor Exhausted) in EESR resister after
the interrupt on.
Rev. 2.00, 03/05, page 461 of 884