SH7615 Datasheet, PDF (18/925 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH
RISC engine Family/SH7600 Series

Item
Page Revisions (See Manual for Details)
14.2.11 FIFO Data Count 594
Register (SCFDR)
Description amended
SCFDR is initialized to H'0000 by a reset, by the module
standby function, and in standby mode.
14.3.2 Operation in
601
Asynchronous Mode
Transmit/Receive Format
Table 14.10 Serial
Transmit/Receive Formats
(Asynchronous Mode)
Table 14.10 amended
SCSMR Settings
Serial Transmit/Receive Format and Frame Length
CHR PE MP STOP 1 2 3 4 5 6 7 8 9 10 11 12
1
00 0
S
7-bit data
STOP
1
S
7-bit data
STOP STOP
1
0
S
7-bit data
P STOP
1
S
7-bit data
P STOP STOP
14.3.3 Multiprocessor 613
Communication Function
Figure 14.12 Sample
Multiprocessor Serial
Transmission Flowchart
Figure 14.12 amended
Yes
Read TEND bit in SC1SSR
No
TEND = 1?
Figure 14.14 Sample 616
Multiprocessor Serial
Reception Flowchart (1)
Figure 14.14 (1) amended
BRK ∨ DR ∨ ER ∨ FER ∨
Yes
ORER = 1?
No
Read RDF flag in SC1SSR
No
RDF = 1?
[3]
Yes
Read receive data from SCFRDR,
and clear RDF flag to 0 in SC1SSR
No
This station’s ID?
[4]
Yes
Read BRK, DR, ER, and FER bits
in SC1SSR, and ORER bit in SC2SSR
BRK ∨ DR ∨ ER ∨ FER ∨
Yes
ORER = 1?
No
14.3.4 Operation in
Synchronous Mode
619 Description amended
In synchronous mode, the SCIF receives data in
synchronization with the rising edge of the serial clock.
Rev. 2.00, 03/05, page xviii of xxxviii