SH7615 Datasheet, PDF (726/925 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH
RISC engine Family/SH7600 Series

16.4 Operation
16.4.1 Overview
Operation in each mode is outlined below.
Normal Operation: Each channel has a TCNT and TGR register. TCNT performs up-counting,
and is also capable of free-running operation, synchronous counting, and external event counting.
Each TGR can be used as an input capture register or output compare register.
Synchronous Operation: The TCNT counter for a channel designated for synchronous operation
by means of TSYR performs synchronous presetting. That is, when TCNT for a channel
designated for synchronous operation is rewritten, the TCNT counters for the other channels are
also rewritten at the same time. Synchronous clearing of the TCNT counters is also possible by
setting the counter clear bits in TCR for channels designated for synchronous operation.
Buffer Operation
• When TGR is an output compare register
When a compare match occurs, the value in the buffer register for the relevant channel is
transferred to TGR.
• When TGR is an input capture register
When input capture occurs, the value in TCNT is transfer to TGR and the value previously
held in TGR is transferred to the buffer register.
PWM Mode: In this mode, a PWM waveform is output. The output level can be set by means of
TIOR. A PWM waveform with a duty of between 0% and 100% can be output, according to the
setting of each TGR register.
Phase Counting Mode: In this mode, TCNT is incremented or decremented by detecting the
phases of two clocks input from the external clock input pins in channels 1, and 2. When phase
counting mode is set, the corresponding TCLK pin functions as the clock input, and TCNT
performs up- or down-counting.
This can be used for two-phase encoder pulse input.
Rev. 2.00, 03/05, page 688 of 884