SH7615 Datasheet, PDF (825/925 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH
RISC engine Family/SH7600 Series

20.4.2 Canceling Standby Mode
Standby mode is canceled by an NMI interrupt, a power-on reset, or a manual reset.
Cancellation by an NMI Interrupt: When a rising edge or falling edge is detected in the NMI
signal, after the elapse of the time set in the WDT timer control/status register, clocks are supplied
to the entire chip, standby mode is canceled, and NMI exception handling begins. Insure that the
interval set for the WDT is at least as long as the oscillation stabilization time. When standby
mode is canceled by a falling edge in the NMI signal, insure that the NMI pin goes high when
standby mode is entered (when the clock is halted), and goes low on recovering from standby
mode (when the clock starts after oscillation has stabilized). The low level at the NMI pin should
be held for at least 3 cycles after the start of clock signal output from the CKIO pin. When standby
mode is canceled by a rising edge in the NMI signal, insure that the NMI pin goes low when
standby mode is entered (when the clock is halted), and goes high on recovering from standby
mode (when the clock starts after oscillation has stabilized). The high level at the NMI pin should
be held for at least 3 cycles after the start of clock signal output from the CKIO pin.
Cancellation by a Power-On Reset: A power-on reset cancels standby mode.
Cancellation by a Manual Reset: A manual reset cancels standby mode.
20.4.3 Standby Mode Cancellation by NMI Interrupt
The following example describes moving to the standby mode upon the fall of the NMI signal and
clearing the standby mode when the NMI signal rises. Figure 20.1 shows the timing.
When the NMI pin level changes from high to low after the NMI edge select bit (NMIE) of the
interrupt control register (ICR) has been set to 0 (detect falling edge), an NMI interrupt is
accepted. When the NMIE bit is set to 1 (detect rising edge) by the NMI exception service routine,
the standby bit (SBY) of the standby control register 1 (SBYCR1) is set to 1 and a SLEEP
instruction is executed, the standby mode is entered. The standby mode is cleared the next time the
NMI pin level changes from low level to high level. The high level at the NMI pin should be held
for at least 3 cycles after the start of clock signal output from the CKIO pin.
Rev. 2.00, 03/05, page 787 of 884