SH7615 Datasheet, PDF (31/925 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH
RISC engine Family/SH7600 Series

8.6 Usage Notes ...................................................................................................................... 376
8.6.1 Standby ................................................................................................................ 376
8.6.2 Cache Control Register........................................................................................ 376
Section 9 Ethernet Controller (EtherC)......................................................................... 377
9.1 Overview........................................................................................................................... 377
9.1.1 Features................................................................................................................ 377
9.1.2 Configuration....................................................................................................... 378
9.1.3 Input/Output Pins................................................................................................. 380
9.1.4 Ethernet Controller Register Configuration......................................................... 381
9.2 Register Descriptions........................................................................................................ 382
9.2.1 EtherC Mode Register (ECMR) .......................................................................... 382
9.2.2 EtherC Status Register (ECSR) ........................................................................... 385
9.2.3 EtherC Interrupt Permission Register (ECSIPR) ................................................. 386
9.2.4 PHY Interface Register (PIR) .............................................................................. 387
9.2.5 MAC Address High Register (MAHR) ............................................................... 388
9.2.6 MAC Address Low Register (MALR)................................................................. 389
9.2.7 Receive Frame Length Register (RFLR) ............................................................. 390
9.2.8 PHY Interface Status Register (PSR) .................................................................. 391
9.2.9 Transmit Retry Over Counter Register (TROCR) ............................................... 392
9.2.10 Collision Detect Counter Register (CDCR)......................................................... 393
9.2.11 Lost Carrier Counter Register (LCCR)................................................................ 394
9.2.12 Carrier Not Detect Counter Register (CNDCR) .................................................. 395
9.2.13 Illegal Frame Length Counter Register (IFLCR)................................................. 396
9.2.14 CRC Error Frame Counter Register (CEFCR) .................................................... 397
9.2.15 Frame Receive Error Counter Register (FRECR )............................................... 398
9.2.16 Too-Short Frame Receive Counter Register (TSFRCR) ..................................... 399
9.2.17 Too-Long Frame Receive Counter Register (TLFRCR ) .................................... 400
9.2.18 Residual-Bit Frame Counter Register (RFCR) .................................................... 401
9.2.19 Multicast Address Frame Counter Register (MAFCR) ....................................... 402
9.3 Operation .......................................................................................................................... 403
9.3.1 Transmission........................................................................................................ 403
9.3.2 Reception ............................................................................................................. 405
9.3.3 MII Frame Timing ............................................................................................... 407
9.3.4 Accessing MII Registers...................................................................................... 409
9.3.5 Magic Packet Detection....................................................................................... 412
9.3.6 CPU Operating Mode and Ethernet Controller Operation................................... 413
9.4 Connection to PHY-LSI.................................................................................................... 414
9.5 Usage Notes ...................................................................................................................... 416
Section 10 Ethernet Controller Direct Memory Access Controller
(E-DMAC) ....................................................................................................... 417
10.1 Overview........................................................................................................................... 417
Rev. 2.00, 03/05, page xxxi of xxxviii