SH7615 Datasheet, PDF (400/925 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH
RISC engine Family/SH7600 Series

Bit 1—Instruction Replacement Disable Bit (ID): ID is the bit for disabling instruction
replacement. When this bit is 1, an instruction fetched from external memory is not written to the
cache even if there is a cache miss. Cache data is, however, read or updated during cache hits. ID
is valid only when CE is 1.
Bit 1: ID
0
1
Description
Normal operation
(Initial value)
Data not replaced even when cache miss occurs in instruction fetch
Bit 0—Cache Enable Bit (CE): CE is the cache enable bit. Cache can be used when CE is set to 1.
Bit 0: CE
0
1
Description
Cache disabled
Cache enabled
(Initial value)
8.3 Address Space and the Cache
The address space is divided into six partitions. The cache access operation is specified by
addresses. Table 8.2 lists the partitions and their cache operations. For more information on
address spaces, see section 7, Bus State Controller. Note that the spaces of the cache area and
cache-through area are the same.
Table 8.2 Address Space and Cache Operation
Addresses
A31 to A29 Partition
000
Cache area
001
Cache-through area
010
Associative purge area
011
Address array read/write area
110
Data array read/write area
111
I/O area
Cache Operation
Cache is used when the CE bit in CCR is 1
Cache is not used
Cache line of the specified address is purged
(disabled)
Cache address array is accessed directly
Cache data array is accessed directly
Cache is not used
Rev. 2.00, 03/05, page 362 of 884