SH7615 Datasheet, PDF (888/925 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH
RISC engine Family/SH7600 Series

21.3.9 High-Performance User Debugging Interface Timing
Table 21.14 High-Performance User Debugging Interface Timing
Conditions: V_CC = PLLV_CC = 3.3 V ±0.3 V, PV_CC = 5.0 V ± 0.5 V/3.3 V ±0.3 V, PV_CC ≥ V_CC,
V_SS = PV_SS = PLLV_SS = 0 V, Ta = –20 to +75°C
Item
Symbol Min
TCK clock input cycle time
t_tcyc
t_Pcyc or^*
66.7 ns
TCK clock input high-level width
t_TCKH
0.4
TCK clock input low-level width
TRST pulse width
TRST setup time
t_TCKL
0.4
t_TRSW
20
t_TRSS
40
TMS setup time
t_TMSS
30
TMS hold time
t_TMSH
10
TDI setup time
t_TDIS
30
TDI hold time
t_TDIH
10
TDO delay time
t_TDOD
0
Note: * Specified as tPcyc or 66.7, whichever is greater.
Max
—
0.6
0.6
—
—
—
—
—
—
30
Unit
ns
t_tcyc
t_tcyc
t_tcyc
ns
ns
ns
ns
ns
ns
Figure
21.65
21.66
21.67
TCK
t_TCKH
t_tcyc
t_TCKL
Figure 21.65 H-UDI Clock Timing
TCK
t_TRSS
t_TRSS
TRST
t_TRSW
Figure 21.66 H-UDI TRST Timing
Rev. 2.00, 03/05, page 850 of 884