SH7615 Datasheet, PDF (158/925 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH
RISC engine Family/SH7600 Series

jmp @r5
nop
nop
nop
nop
nop
clock4_err:
bra clock4_err
nop
nop
nop
nop
;
;
Main portion of frequency change code.
;
First copy this to XRAM and then run it in XRAM.
FREQUENCY:
; <Watchdog timer control and status register setting>
; Clear TME bit.
; Clock input to WTCNT is φ/16384
; (Overflow frequency = 262.144 ms)
MOV.W R2,@R1
; <External cache through area read>
; Cache through area of external member space 3: H'26200000
MOV.L @R3,R0
; <Frequency change register setting>
; PLL circuit 1 → Disabled.
; PLL circuit 2 → Enabled.
; Iφ (×4) = 62.5 MHz, Eφ (×4) = 62.5 MHz,
; Pφ (×2) = 31.25 MHz, CKIO (Eφ) = 62.5 MHz,
; MOV #H'4E,R0
; PLL circuits 1 and 2 → Enabled.
; Iφ (×4) = 62.5 MHz, Eφ (×2) = 31.25 MHz,
; Pφ (×2 ) = 31.25 MHz, CKIO (Eφ) = 31.25 MHz,
MOV #H'0A,R0
Rev. 2.00, 03/05, page 120 of 884