SH7615 Datasheet, PDF (19/925 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH
RISC engine Family/SH7600 Series

Item
Page Revisions (See Manual for Details)
14.5 Usage Notes
640 SCIF Initialization Flowchart and Receive-FIFO-Data-Full
Interrupt (RXI) Requests added
17.1.2 H-UDI Block
Diagram
732 Figure 17.1 amended
Figure 17.1 H-UDI Block
Diagram
SDIR
SDSR
SDDRH
SDDRL
SDIDR
17.1.4 Register
733
Configuration
Table 17.2 Register
Configuration
17.3.2 Status Register 737
(SDSR)
17.3.6 ID Code Register 750
(SDIDR)
17.4.1 TAP Controller 751
Figure 17.2 TAP
Controller State
Transitions
Table 17.2 amended
Register
Instruction register
Status register
Data register H
Data register L
ID code register
Abbreviation R/W^*1
SDIR
R
SDSR
R/W
SDDRH
R/W
SDDRL
R/W
SDIDR
—
Initial Value^*2
H'E000
H'0401
Undefined
Undefined
H'0101000F
Address
H'FFFFFCB0
H'FFFFFCB2
H'FFFFFCB4
H'FFFFFCB6
—
Access Size
(Bits)
8/16/32
8/16
8/16/32
8/16
—
Bit table amended
Bit: 15
14
13
12
11
10
9
8
—
—
—
—
—
—
—
—
Initial value
0
0
0
0
0
1
0
0
R/W: R
R
R
R
R
R
R
R
Description amended
The ID code register (SDIDR) is a 32-bit register. In the
IDCODE mode, SDIDR can output H'0101000F, which is a
fixed code, from TDO.
Description amended
Figure 17.2 shows the internal states of TAP controller. State
transitions basically conform with the IEEE1149.1 standard.
Figure 17.2 amended
1 Test-logic-reset
0
1
0 Run-test/idle
1
Select-DR-scan
0
1
Select-IR-scan
Rev. 2.00, 03/05, page xix of xxxviii