SH7615 Datasheet, PDF (391/925 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH
RISC engine Family/SH7600 Series

CKIO
BRLS
BGR
Address data
CSn
Other bus
control signals
Figure 7.58 Bus Arbitration
7.10 Additional Items
7.10.1 Resets
The bus state controller is completely initialized only in a power-on reset. All signals are
immediately negated, regardless of whether or not the chip is in the middle of a bus cycle. Signal
negation is simultaneous with turning the output buffer off. All control registers are initialized. In
standby mode, sleep mode, and a manual reset, no bus state controller control registers are
initialized. When a manual reset is performed, the currently executing bus cycle only is completed,
and then the chip waits for an access. When a cache-filling or DMAC/E-DMAC 16-byte transfer is
executing, the CPU, DMAC, or E-DMAC that is the bus master ends the access in a longword
unit, since the access request is canceled by the manual reset. This means that when a manual reset
is executed during a cache filling, the cache contents can no longer be guaranteed. During a
manual reset, the RTCNT does not count up, so no refresh request is generated, and a refresh cycle
is not initiated. To preserve the data of the DRAM and synchronous DRAM, the pulse width of the
manual reset must be shorter than the refresh interval. Master mode chips accept arbitration
requests even when a manual reset signal is asserted. When a reset is executed only for the chip in
master mode while the bus is released, the BGR signal is negated to indicate this. If the BRLS
signal is continuously asserted, the bus release state is maintained.
7.10.2 Access as Viewed from CPU, DMAC or E-DMAC
The chip is internally divided into three buses: cache, internal, and peripheral. The CPU and cache
memory are connected to the cache bus, the DMAC, E-DMAC and bus state controller are
connected to the internal bus, and the low-speed peripheral devices and mode registers are
connected to the peripheral bus. On-chip memory other than cache memory and the user break
controller are connected to both the cache bus and the internal bus. The internal bus can be
accessed from the cache bus, but not the other way around. The peripheral bus can be accessed
from the internal bus, but not the other way around. This results in the following.
Rev. 2.00, 03/05, page 353 of 884