SH7615 Datasheet, PDF (508/925 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH
RISC engine Family/SH7600 Series

11.2.4 DMA Channel Control Registers 0 and 1 (CHCR0, CHCR1)
Bit: 31
30
29
…
19
18
17
16
—
—
—
…
—
—
—
—
Initial value: 0
0
0
…
0
0
0
0
R/W: R
R
R
…
R
R
R
R
Bit: 15
14
13
12
11
10
9
8
DM1 DM0 SM1
SM0
TS1
TS0
AR
AM
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 7
6
5
4
3
2
1
0
AL
DS
DL
TB
TA
IE
TE
DE
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/(W)^* R/W
Note: * Only 0 can be written, to clear the flag.
DMA channel control registers 0 and 1 (CHCR0 and CHCR1) are 32-bit read/write registers that
control the DMA transfer mode. They also indicate the DMA transfer status. Only the lower 16 of
the 32 bits are valid. They should be read and written as 32-bit values, including the upper 16 bits.
The registers are initialized to H'00000000 by a reset and in standby mode. Values are retained
during a module standby.
Bits 31 to 16—Reserved: These bits are always read as 0. The write value should always be 0.
Bits 15 and 14—Destination Address Mode Bits 1, 0 (DM1, DM0): Select whether the DMA
destination address is incremented, decremented or left fixed (in single address mode, DM1 and
DM0 are ignored when transfers are made from a memory-mapped external device, or external
memory to an external device with DACK). DM1 and DM0 are initialized to 00 by a reset and in
standby mode. Values are retained during a module standby.
Rev. 2.00, 03/05, page 470 of 884