SH7615 Datasheet, PDF (399/925 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH
RISC engine Family/SH7600 Series

Bit 5—Write-Back Bit (WB): Specifies the cache operation method when the cache area is
accessed.
Bit 5: WB
0
1
Description
Write-through
Write-back
(Initial value)
Bit 4—Cache Purge Bit (CP): When 1 is written to the CP bit, all cache entries and the valid bits,
and LRU information of all ways are initialized to 0. After initialization is completed, the CP bit
reverts to 0. The CP bit always reads 0. Read the cache to check if initialization is completed.
Bit 4: CP
Description
0
Normal operation
1
Cache purge
Note: Always read 0.
(Initial value)
Bit 3—Two-Way Mode (TW): TW is the two-way mode bit. The cache operates as a four-way set
associative cache when TW is 0 and as a two-way set associative cache and 2-kbyte RAM when
TW is 1. In the two-way mode, ways 2 and 3 are cache and ways 0 and 1 are RAM. Ways 0 and 1
are read or written by direct access of the data array according to address space specification.
Bit 3: TW
0
1
Description
Four-way mode
Two-way mode
(Initial value)
Bit 2—Data Replacement Disable Bit (OD): OD is the bit for disabling data replacement. When
this bit is 1, data fetched from external memory is not written to the cache even if there is a cache
miss. Cache data is, however, read or updated during cache hits. OD is valid only when CE is 1.
Bit 2: OD
0
1
Description
Normal operation
(Initial value)
Data not replaced even when cache miss occurs in data access
Rev. 2.00, 03/05, page 361 of 884